"By delivering the first discrete timing solution for PCIe Gen 6, Renesas is enabling customers to develop the next-generation of high-performance systems," said Rich Wawrzyniak, principal analyst for Semico Research in a statement from Renesas. Developers of next-generation server platforms may be able to begin designing motherboards, accelerators, network cards, and SSDs as a result of this. Meanwhile, designing and testing ultra-complex PCIe Gen 6 circuits will take time, so the sooner hardware developers begin developing new products, the better. However, in a data center, bandwidth is everything.
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The new chips complement Renesas' low-jitter 9SQ440, 9FGV1002, and 9FGV1006 clock generators, allowing the company to provide a full PCIe 6.0 timing solution.Ĭonsumer graphics cards and solid-state drives are unlikely to require 256 GBps bi-directional bandwidth over a 16-lane interface or 64 GBps bi-directional bandwidth over a 4-lane interface any time soon. The new clock buffers also have a 1.4 ns in-out delay, a 35ps out-of-out skew, and a -80dB power supply rejection ratio (PSRR) at 100kHz. Renesas is introducing 11 new RC190xx clock buffers and four new RC192xx multiplexers with additive jitter of only 4fs RMS, making them virtually noiseless, a feature critical for PCIe Gen6 applications. The new devices will enable companies to create motherboards and other devices that should meet PCIe 6.0 performance and signal integrity requirements while also being compatible with PCIe 5.0 applications.
Renesas has introduced the industry's first lineup of PCIe 6.0-compliant clock buffers and multiplexers.
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